Particular embodiments generally relate to digitally controlled oscillators (DCOs).
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A digitally controlled oscillator (DCO) is used in systems including an all-digital phase lock loop (DLL), frequency lock loop (FLL), or in DLLs that perform clock synthesis and data recovery. In one example, the DCO is used in the all-digital DLL to generate a radio frequency (RF) signal with a frequency proportional to a reference clock.
FIG. 1 shows an example of a conventional PLL 100. A DCO 102 generates the RF signal (fosc) with a frequency proportional to a reference clock (fref). The output of DCO 102 is divided by a frequency divider 104. The output of frequency divider 104 is input into a time digital converter (TDC) 106. TDC 106 receives the reference clock and the divided frequency signal and determines an error between the reference clock and the divided frequency signal. The error is output to a low pass loop filter 108, which produces a digital word that is input into DCO 102. DCO 102 uses the digital word to generate the RF signal.
FIG. 2 shows an example of a conventional DCO 200. An inductor-capacitor (LC) tank 202 includes an inductor 204 (Ltank) and capacitor (Ctank) 206. A tuning capacitor 208, a pair of cross-coupled transistors (M1 and M2) 214, and a bias current source (Ib) 210 are also provided. Tuning capacitor 208 is tuned to adjust the frequency that is output from LC tank 202. A resistance loss (resistor Rloss 209) models the losses of inductor 204 and capacitor 206. Cross-coupled pair of transistors M1 and M2 introduce a negative resistance (−R) that compensates for the losses of LC tank 202 and keeps an output signal of DCO 200 oscillating.
FIG. 3 shows a model of DCO 200. The negative resistance −R is shown in parallel with inductor 204, capacitor 206, tuning capacitor 208, and the resistor 209. The capacitance of tuning capacitor 208 is adjusted using a capacitor bank present in LC tank 202. For example, the following equations are used to adjust the frequency:
            f      osc        =                            1                      2            ⁢                                                  ⁢            π            ⁢                                                            C                  tank                                ⁢                                  L                  tank                                                                    ⁢        △        ⁢                                  ⁢                  f          osc                    =                        -                      f            osc                          ·                              △            ⁢                                                  ⁢                          C              tank                                2                      ,where fosc is the output signal of DCO 200 (or LC tank 202), Δ fosc is the frequency variation of the output signal, and ΔCtank is the variance of the tuning capacitance of tuning capacitor 208. For example, if a 2 kHz frequency resolution at 3.3 GHz is desired where the capacitance value of capacitor 206 is Ctank=4.5 pF and the inductance value of inductor 204 is L=500 pH, then tuning capacitor 208 has a tuning capacitance of ΔCtank=5 actoFarads (aF). ΔCtank may be the value of each capacitor in the capacitor bank. In this case, the tuning capacitance is a capacitance that is smaller than technology can implement effectively.
One solution for solving the problem of having a tuning capacitance that is too small to implement is to use dithering. FIG. 4a shows an example of a DCO model 400 using a dithering implementation. An equivalent capacitance ΔCeq seen by LC tank 202 is less than a capacitance (ΔC) 402 because of the dithering being applied using a digital switch 410. Referring to FIG. 4b, switching at a high frequency between two capacitances, Ctank and ΔC, provides an equivalent capacitance ΔCeq.
FIG. 4b shows a signal 404 output by a digital ΣΔ 408 of FIG. 4a. When signal 404 is low, the capacitance is Ctank. When signal 404 is high, the capacitance is ΔC+Ctank. A time 406 when the capacitance is ΔC+Ctank is a time Td and a time for a period of signal 404 is Tr. Td/Tr is the time in which a capacitance ΔC is added to the capacitance Ctank. This yields an equivalent capacitance shown by the equation:
      C    eq    =            C      tank        +          △      ⁢                          ⁢      C      ⁢                                    T            d                                T            r                          .            
In the implementation of FIG. 4a, a signal fdth is input into digital ΣΔ 408. Digital ΣΔ 408 takes an 8 bit signal and outputs a 3-bit signal 404 that is used to open and close a switch 410. Dithering of the 3 less significant bits of the 8 bit signal is provided. The value for ΔC is larger than a capacitance of around an aF, but dithering lowers the equivalent capacitance ΔCeq that is seen from the physical capacitances implemented by capacitor 402.
Dithering may lower the equivalent capacitance and allow larger capacitances to be used, but noise is increased from the 3 bit signal. The quantization noise is moved to higher frequencies where generally the noise-phase specifications are more challenging. Due to this problem, the frequency of dithering may be significantly increased.